Samsung Electronics announced a major cooperation on July 9th - Preferred Networks (PFN), an emerging force in Japan's AI field, has officially commissioned Samsung to produce AI chips using a 2-nanometer wafer process and advanced 2.5D Interposer Cube S (I-Cube S) packaging technology. This milestone cooperation not only marks Samsung's first public acceptance of wafer foundry orders for the 2-nanometer process, but also heralds an unprecedented performance and energy efficiency revolution in the AI chip field.

Looking back to the end of 2023, South Korean media have revealed that Samsung's wafer foundry business has won a mysterious order for 2-nanometer AI chips, and the announcement of this cooperation partner undoubtedly threw a shock wave to the industry. Preferred Networks， As a leader in Japan's AI field, known for its innovative technological strength and forward-looking market layout, this partnership with Samsung will undoubtedly provide more solid computing power support for its generative AI, especially in the field of large language models.

The 2-nanometer SF2 process technology adopted by Samsung Electronics this time is its latest achievement in the field of semiconductor technology. According to Samsung's official introduction, compared to its second-generation 3GAP 3-nanometer process, this process can achieve a power consumption reduction of up to 25% at the same operating frequency and complexity. While maintaining the same power consumption and complexity, the computing performance can be improved by 12%, and the chip area can also be reduced by 5%. This series of technological breakthroughs undoubtedly opens up a new path for AI chips to pursue the ultimate performance and energy efficiency ratio.

Of particular note, Samsung also provided its exclusive 2.5D I-Cube S heterogeneous integrated packaging solution for this collaboration. This technology efficiently integrates multiple chips into a single package, not only significantly improving the interconnection speed between chips, but also greatly reducing the package size, providing AI chips with a more compact and efficient phySICal form while pursuing high performance, further meeting the stringent requirements of generative AI for computing power density and energy efficiency.

For this collaboration, Junichiro Makino, Vice President and Chief Technology Officer of PFN's Computing Architecture Department, expressed high expectations and confidence: "We are honored to collaborate with industry leaders like Samsung Electronics, using their cutting-edge 2-nanometer GAA process technology. We believe that this collaboration will greatly promote the development of AI chips and help us meet the growing computing power demand in the field of generative AI, especially in the area of big language models, and jointly create a new chapter in AI technology

In summary, the collaboration between Samsung Electronics and Preferred Networks is not only a strong technical alliance, but also a profound insight and layout into the future trends of the AI computing power market. With the implementation of the 2-nanometer process and advanced packaging technology, we have reason to believe that a more efficient, energy-saving, and powerful AI computing era is accelerating.